general description features ics9148-13 block diagram pentium is a trademark of intel corporation frequency generator & integrated buffers for pentium tm 9148-13 rev a 020398 pin configuration the ics9148-13 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentium and pentiumpro. an output enable is provided for testability. spread spectrum is available to modulate the cpu and bus pll (leaving the ref, 24, 48 mhz operating normally). the ss_en# pin enables the spreading when low. the ss_type pin choses 0.5% (nominally) center spread or +0, -2% (nominally) downspread modulation. high drive bus outputs typically provide greater than 1 v/ns slew rate into 30 pf loads. cpu outputs typically provide better than 1v/ns slew rate into 20 pf loads while maintaining 50 5% duty cycle. the ref clock outputs typically provide better than 0.8/ns slew rates. generates twelve processor, six bus, two 14.31818mhz, 24mhz and one 48mhz clock for usb support. synchronous clocks skew matched to 250 ps window on cpus and 500 ps window on buss ? cpu to bus skew, 3.0 to 5.0ns (cpu early) 3.0v - 3.7v supply range 48-pin ssop package 48-pin ssop functionality 2s f1 s f0 sf ni)21:1(upc zhm ni)6:1(sub zhm 000 5 75 .73 001 0 0 13 .33 010 5 70 .03 011 3 .3 85 6.14 100 0 55 2 10 1 0 60 3 110 7 6.6 63 3.33 111 5 55 .72 e of er 42 )zhm( 84 )zhm( up cs u bo c vc so 1s nu rs nu rs nu rs nu rs nu rs nu rs nur 0 -irt etats -irt etats -irt etats -irt etats -irt etats snu rs nur output enable 30k pullup resistor to vdd on oe, fs(0:2), ss_en#, ss_type ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9148-13 pin descriptions spread spectrum functionality 9 1 n i p t u p n i # n e _ s s 0 2 n i p t u p n i e p y t _ s s m a r d s , u p c s k c o l c i c p d n a c i p a o i , f e rz h m 4 2z h m 8 4 0 0 n i d e t a l u d o m y c n e u q e r f e d o m m u r t c e p s d a e r p s ) y l l a n i m o n ( % 5 . 0 - , % 5 . 0 + z h m 8 1 3 . 4 1z h m 4 2z h m 8 4 1 n i d e t a l u d o m y c n e u q e r f e d o m m u r t c e p s d a e r p s ) y l l a n i m o n ( % 0 . 2 - , % 0 + z h m 8 1 3 . 4 1z h m 4 2z h m 8 4 1x y c n e u q e r f y d a e t s , l a m r o n e d o m z h m 8 1 3 . 4 1z h m 4 2z h m 8 4 r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 2 , 12 f e r , 1 f e rt u o. s t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , 0 1 , 3, 4 2 , 8 1 4 4 , 3 4 , 5 3 , 0 3 d n gr w pd n u o r g e c i v e d 41 xn i. t u p n i k c o l c l a n r e t x e r o l a t s y r c 52 xt u o) d e t c e n n o c n u e v a e l k c o l c e c n e r e f e r l a n r e t x e r o f ( . t u p t u o l a t s y r c 6d d vr w pv 3 . 3t l o v. y l p p u s r e w o p o / i 7 2 , 6 2 , 7) 2 : 0 ( s fn is r o t s i s e r p u l l u p s a h . e l b a t t s i l n o i t c n u f e e s . s t u p n i t c e l e s y c n e u q e r f 7 1 , 6 1 , 4 1 , 3 1 , 2 1 , 1 1) 6 : 1 ( s u bt u o. s t u p t u o k c o l c s u b 9 1# n e _ s sn i. e l b a n e = w o l . e l b a n e m u r t c e p s d a e r p s 0 2e p y t _ s sn i . d a e r p s n w o d m u r t c e p s d a e r p s = h g i h . d a e r p s r e t n e c m u r t c e p s d a e r p s = w o l , 2 3 , 1 3 , 8 2 , 1 2 , 5 1 8 4 , 6 4 , 0 4 d d vr w pv 3 . 3 . y l p p u s r e w o p e r o c 2 2z h m 4 2t u ot u p t u o k c o l c z h m 4 2 3 2z h m 8 4t u o. t u p t u o k c o l c z h m 8 4 5 2c / nt c e n n o c o n 9 2e on i u p c , s k c o l c d e x i f , s k c o l c s u b l l a w o l s i l a n g i s s i h t n e h w e l b a n e t u p t u o ) p u d e l l u p y l l a n r e t n i ( e d o m e t a t s i r t n i d e c a l p s t u p t u o s k c o l c , 8 3 , 7 3 , 6 3 , 4 3 , 3 3 , 8 , 7 4 , 5 4 , 2 4 , 1 4 , 9 3 9 ) 2 1 : 1 ( u p ct u o y c n e u q e r f r o f e l b a t y t i l a n o i t c n u f e e s s t u p t u o s k c o l c u p c s n o i t a c i f i c e p s vdd pins: 48, refs, xtal osc vdd pins: 6, cpu 1- 2 vdd pins: 15, bus 1-6 vdd pins: 24, 48, fix pll vdd pins: 28, cpu pll core vdd pins: 32, cpu 3-6 vdd pins: 40, cpu 7-10 vdd pins: 46, cpu 11-12
ics9148-13 absolute maximum ratings supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih1 v in = v dd; ss_type only 68.0 200 a i ih2 v in = v dd; all outputs except ss_type -5 0.2 5 a input low current i il1 v in = 0 v;with pull-down resistors ss_type only -5 0.2 5 a i il2 v in = 0 v;with pull-up resistors except ss_type -200 -100 a supply current i dd c l = 0 pf; select @ 66m 67 180 ma input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 1.5 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cp u-bus v t = 1.5 v; 3.0 4.0 5.0 ns 1 guarenteed by design, not 100% tested in production.
ics9148-13 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2a 1 v o = v dd *(0.5) 10 20 ? output impedance r dsn2a 1 v o = v dd *(0.5) 10 20 ? output high voltage v oh2a i oh = -28 ma 2.4 2.5 v output low voltage v ol2a i ol = 27 ma 0.35 0.4 v output high current i oh2a v oh = 2.0 v -52 -48 ma output low current i ol2a v ol = 0.8 v 49.3 59 ma ris e time t r2a 1 v ol = 0.8 v, v oh = 2.4 v 1.5 2.5 ns fall time t f2 a 1 v oh = 2.4 v, v ol = 0.8 v 1.3 2 ns duty cycle d t2a 1 v t = 1.5 v 45 51 55 % skew t sk2a 1 v t = 1.5 v 120 250 ps jitter t j1s2a 1 v t = 1.5 v 60 150 ps t jabs2a 1 v t = 1.5 v; for 66.66 mhz and lower -250 100 +250 ps t jabs2a 1 v t = 1.5 v; for 75 mhz and higher -300 150 -300 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 24m, 48m, ref(1:2) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = -8 ma 2.6 2.9 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma ris e time t r5 1 v ol = 0.8 v, v oh = 2.4 v 2.0 2.5 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.8 v 1.8 2.3 ns duty cycle d t5 1 v t = 1.5 v 40 53 60 % jitter t j1s5 1 v t = 1.5 v 200 300 ps t jabs5 1 v t = 1.5 v -700 500 700 ps 1 guarenteed by design, not 100% tested in production.
ics9148-13 electrical characteristics - bus t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -11 ma 2.4 3 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -22 ma output low current i ol1 v ol = 0.8 v 16 46 ma ris e time t r1 1 v ol = 0.8 v, v oh = 2.4 v 1.7 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.8 v 1.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 200 500 ps jitter t j1s1 1 v t = 1.5 v 30 150 ps t jabs1 1 v t = 1.5 v -250 110 250 ps 1 guarenteed by design, not 100% tested in production.
ics9148-13 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3. optional crystal load capacitors are recommended capacitor values: c1, c2: crystal load values determined by user. all unmarked capacitors are 0.01f ceramic
ics9148-13 ordering information ics9148f-13 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp this table in inches ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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